Desarrollo e implementación de Circuitos Correctores de Errores de baja redundancia para Sistemas Empotrados Distribuidos Reconfigurables

Welcome to the blog of the research project «Desarrollo e implementación de Circuitos Correctores de Errores de baja redundancia para Sistemas Empotrados Distribuidos Reconfigurables», funded by the UPV through the program «Primeros Proyectos de Investigación (PAID-06-18)», Vicerrectorado de Investigación, Innovación y Transferencia de la Universitat Politècnica de València (UPV), under the project 200190032.

In this blog, we will inform you about all novelties produced during the development of the DIECC-SEDR project.

Abstract:

In recent years, technological development has led to an increase in the performance of digital systems at the cost of reducing their reliability. For example, thanks to the continuous reduction in the size of CMOS technology, current memory systems provide a large storage capacity. However, this decrease in size also causes an increase in its failure rate. In this sense, the impact of a cosmic radiation particle can cause the change in a single memory cell (event known as Single Cell Upset or SCU) or, as shown in different experiments, in several memory cells (Multiple Cell Upset or MCUs), that is, simultaneous errors in more than one memory cell induced by a single particle.

Traditionally, Error Correction Codes (ECC) has been used to protect memories. The most commonly used codes have been SEC codes or SEC-DED codes. SEC codes can correct an error in a single memory cell, while SEC-DED codes can correct an error in a memory cell, and detect two errors in two independent cells. In critical applications, more complex and sophisticated codes are used. However, when adding an ECC to a memory system, we must consider the required redundancy, that is, the additional bits that are used to detect and/or correct the possible errors produced and that are added to each word of data stored in the memory. In this way, the amount of storage occupied by the redundant bits is scaled with the memory capacity. On the other hand, the complexity of the coding and decoding circuits will affect the overheads introduced with respect to area, power conssumption and delay.

This project will develop a series of Error Correction Codes whose main characteristic is its low redundancy. To do this, FUEC methodology will be used. Thanks to this methodology, it is possible to develop very efficient ECCs: low redundancy, high error coverage, etc. Once these new ECCs were designed, we will check their error coverage through simjulation based fault injection. Finally, the different ECCs will be synthesized in CMOS technology, in order to check, as accurately as possible, the overheads introduced with respect to area, power conssumption and delay. In this way, it will be possible to make a complete comparison between the developed ECCs and those ECCs traditionally presented in the literature.