Archive for Paper

Artículo aceptado en IEEE Access

El trabajo titulado «Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection», escrito por Luis-J. Saiz-Adalid, Joaquín Gracia-Morán, Daniel Gil-Tomás, J.-Carlos Baraza-Calvo y Pedro-J. Gil-Vicente ha sido aceptado en la revista IEEE Access. Resumen Reliable computer systems employ error control codes (ECCs) to protect information from errors. For example, memories are frequently protected […]

Comments off

Paper accepted at IEEE Access

The paper entitled «Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection», authored by Luis-J. Saiz-Adalid, Joaquín Gracia-Morán, Daniel Gil-Tomás, J.-Carlos Baraza-Calvo and Pedro-J. Gil-Vicente has been accepted at IEEE Access. Abstract Reliable computer systems employ error control codes (ECCs) to protect information from errors. For example, memories are frequently protected using single […]

Comments off

Artículo disponible en la revista Electronics

El artículo titulado “Fault Modeling of Graphene Nanoribbon FET Logic Circuits”, escrito por D. Gil-Tomàs, J. Gracia-Morán, L.J. Saiz-Adalid y P.J. Gil-Vicente, y publicado por la revista Electronics, está disponible en el siguiente enlace.

Comments off

Paper available at Electronics Journal

The paper entitled “Fault Modeling of Graphene Nanoribbon FET Logic Circuits”, written by D. Gil-Tomàs, J. Gracia-Morán, L.J. Saiz-Adalid and P.J. Gil-Vicente, and published by Electronics Journal, is now available here.

Comments off

Artículo aceptado en la revista Electronics

El artículo titulado “Fault Modeling of Graphene Nanoribbon FET Logic Circuits”, escrito por D. Gil-Tomàs, J. Gracia-Morán, L.J. Saiz-Adalid y P.J. Gil-Vicente ha sido acceptado para su publicación en la Revista Electronics . Resumen: Due to the increasing defect rates in highly scaled complementary metal–oxide–semiconductor (CMOS) devices, and the emergence of alternative nanotechnology devices, reliability […]

Comments off

Paper accepted at Electronics Journal

The paper entitled “Fault Modeling of Graphene Nanoribbon FET Logic Circuits”, written by D. Gil-Tomàs, J. Gracia-Morán, L.J. Saiz-Adalid and P.J. Gil-Vicente has been accepted for publication at Electronics Journal. Abstract: Due to the increasing defect rates in highly scaled complementary metal–oxide–semiconductor (CMOS) devices, and the emergence of alternative nanotechnology devices, reliability challenges are of […]

Comments off

Next entries »