Artículo aceptado en IEEE Access

El trabajo titulado «Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection», escrito por Luis-J. Saiz-Adalid, Joaquín Gracia-Morán, Daniel Gil-Tomás, J.-Carlos Baraza-Calvo y Pedro-J. Gil-Vicente ha sido aceptado en la revista IEEE Access.

Resumen

Reliable computer systems employ error control codes (ECCs) to protect information from errors. For example, memories are frequently protected using single error correction-double error detection (SEC-DED) codes. ECCs are traditionally designed to minimize the number of redundant bits, as they are added to each word in the whole memory. Nevertheless, using an ECC introduces encoding and decoding latencies, silicon area usage and power consumption. In other computer units, these parameters should be optimized, and redundancy would be less important. For example, protecting registers against errors remains a major concern for deep sub-micron systems due to technology scaling. In this case, an important requirement for register protection is to keep encoding and decoding latencies as short as possible. Ultrafast error control codes achieve very low delays, independently of the word length, increasing the redundancy. This paper summarizes previous works on Ultrafast codes (SEC and SEC-DED), and proposes new codes combining double error detection and adjacent error correction. We have implemented, synthesized and compared different Ultrafast codes with other state-of-the-art fast codes. The results show the validity of the approach, achieving low latencies and a good balance with silicon area and power consumption.

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Paper accepted at IEEE Access

The paper entitled «Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection», authored by Luis-J. Saiz-Adalid, Joaquín Gracia-Morán, Daniel Gil-Tomás, J.-Carlos Baraza-Calvo and Pedro-J. Gil-Vicente has been accepted at IEEE Access.

Abstract

Reliable computer systems employ error control codes (ECCs) to protect information from errors. For example, memories are frequently protected using single error correction-double error detection (SEC-DED) codes. ECCs are traditionally designed to minimize the number of redundant bits, as they are added to each word in the whole memory. Nevertheless, using an ECC introduces encoding and decoding latencies, silicon area usage and power consumption. In other computer units, these parameters should be optimized, and redundancy would be less important. For example, protecting registers against errors remains a major concern for deep sub-micron systems due to technology scaling. In this case, an important requirement for register protection is to keep encoding and decoding latencies as short as possible. Ultrafast error control codes achieve very low delays, independently of the word length, increasing the redundancy. This paper summarizes previous works on Ultrafast codes (SEC and SEC-DED), and proposes new codes combining double error detection and adjacent error correction. We have implemented, synthesized and compared different Ultrafast codes with other state-of-the-art fast codes. The results show the validity of the approach, achieving low latencies and a good balance with silicon area and power consumption.

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Presentación en las Jornadas SARTECO 2019

El pasado 18 de Septiembre, J. Gracia-Morán presentó el trabajo titulado «Mejora de un Código de Corrección de Errores para tolerar fallos adyacentes bidimensionales» en las Jornadas SARTECO 2019.

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Presentation at Jornadas SARTECO 2019

Last 18 September, J. Gracia-Morán presented the paper entitled «Mejora de un Código de Corrección de Errores para tolerar fallos adyacentes bidimensionales» at the Jornadas SARTECO 2019.

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Panel en CARS 2019

El pasado 17 de Septiembre, Juan Carlos Ruiz participó en el panel «Autonomous driving: safety and security issues», celebrado durante el 5th International Workshop on Critical Automotive Applications: Robustness & Safety (CARS 2019), en conlaboración con el EDCC 2019 en Nápoles, Italia.

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Panel at CARS 2019

Last September, 17th, Juan Carlos Ruiz took part in the panel «Autonomous driving: safety and security issues», celebrated in the 5th International Workshop on Critical Automotive Applications: Robustness & Safety (CARS 2019), collocated with EDCC 2019 in Naples, Italy.

 

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Presentación en el EDCC 2019

Juan Carlos Ruiz ha presentado el artículo publicado «Robustness-aware design space exploration by iteratively augmenting and repairing D-optimal designs», escrito por Ilya Tuzov, David De Andrés and Juan Carlos Ruiz.

Resumen:

Design space exploration (DSE) is nowadays of utmost importance to implement HW designs with acceptable levels of performance, power consumption, area and dependability (PPAD). Electronic Design Automation (EDA) tools support the transformation of HW description models into technology-dependent implementations. Although designers can influence this process by tuning the parameters offered by EDA toolkits, determining their proper configuration is a complex and very time-consuming DSE problem rarely addressed from a PPAD perspective. On one hand, the spatial and temporal complexity of considered targets and the level of abstraction of their descriptions pose problems for the rapid execution of fault injection campaigns. On the other hand, the multi-level nature of parameters offered by EDA toolkits lead to an explosion of possible configurations to exercise during experimentation. This paper shows how to combine the D-optimal design of experiments with FPGA-based and statistical fault injection to significantly reduce not only the number of such configurations but also the number of faults to inject and the time required to perform each injection. All of this without compromising the statistical significance of results. The proposal is exemplified through the Xilinx Vivado Design Suite, which integrates one of the FPGA-based EDA toolkits most widely-used today in the industry, and the MC8051 IP core, a synthesizable microcontroller from Oregano Systems.

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Presentation at EDCC 2019

Juan Carlos Ruiz has presented the paper entitled «Robustness-aware design space exploration by iteratively augmenting and repairing D-optimal designs», written by Ilya Tuzov, David De Andrés and Juan Carlos Ruiz.

Abstract:

Design space exploration (DSE) is nowadays of utmost importance to implement HW designs with acceptable levels of performance, power consumption, area and dependability (PPAD). Electronic Design Automation (EDA) tools support the transformation of HW description models into technology-dependent implementations. Although designers can influence this process by tuning the parameters offered by EDA toolkits, determining their proper configuration is a complex and very time-consuming DSE problem rarely addressed from a PPAD perspective. On one hand, the spatial and temporal complexity of considered targets and the level of abstraction of their descriptions pose problems for the rapid execution of fault injection campaigns. On the other hand, the multi-level nature of parameters offered by EDA toolkits lead to an explosion of possible configurations to exercise during experimentation. This paper shows how to combine the D-optimal design of experiments with FPGA-based and statistical fault injection to significantly reduce not only the number of such configurations but also the number of faults to inject and the time required to perform each injection. All of this without compromising the statistical significance of results. The proposal is exemplified through the Xilinx Vivado Design Suite, which integrates one of the FPGA-based EDA toolkits most widely-used today in the industry, and the MC8051 IP core, a synthesizable microcontroller from Oregano Systems.

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Artículo disponible en la revista Electronics

El artículo titulado “Fault Modeling of Graphene Nanoribbon FET Logic Circuits”, escrito por D. Gil-Tomàs, J. Gracia-Morán, L.J. Saiz-Adalid y P.J. Gil-Vicente, y publicado por la revista Electronics, está disponible en el siguiente enlace.

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Paper available at Electronics Journal

The paper entitled “Fault Modeling of Graphene Nanoribbon FET Logic Circuits”, written by D. Gil-Tomàs, J. Gracia-Morán, L.J. Saiz-Adalid and P.J. Gil-Vicente, and published by Electronics Journal, is now available here.

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