Paper accepted at Electronics journal

The paper entitled “Reducing the Overhead of BCH Codes: New Double Error Correction Codes”, authored by Luis-J. Saiz-Adalid, Joaquín Gracia-Morán, Daniel Gil-Tomás, J.-Carlos Baraza-Calvo and Pedro-J. Gil-Vicente has been published at Electronics journal.

Abstract

The Bose-Chaudhuri-Hocquenghem (BCH) codes are a well-known class of powerful error correction cyclic codes. BCH codes can correct multiple errors with minimal redundancy. Primitive BCH codes only exist for some word lengths, which do not frequently match those employed in digital systems. This paper focuses on double error correction (DEC) codes for word lengths that are in powers of two (8, 16, 32, and 64), which are commonly used in memories. We also focus on hardware implementations of the encoder and decoder circuits for very fast operations. This work proposes new low redundancy and reduced overhead (LRRO) DEC codes, with the same redundancy as the equivalent BCH DEC codes, but whose encoder, and decoder circuits present a lower overhead (in terms of propagation delay, silicon area usage and power consumption). We used a methodology to search parity check matrices, based on error patterns, in order to design the new codes. We implemented and synthesized them, and compared their results with those obtained for the BCH codes. Our implementation of the decoder circuits achieved reductions between 2.8% and 8.7% in the propagation delay, between 1.3% and 3.0% in the silicon area, and between 15.7% and 26.9% in the power consumption. Therefore, we propose LRRO codes as an alternative for protecting information against multiple errors.

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Artículo aceptado en la revista Electronics

El trabajo titulado “Reducing the Overhead of BCH Codes: New Double Error Correction Codes”, desarrollado por Luis-J. Saiz-Adalid, Joaquín Gracia-Morán, Daniel Gil-Tomás, J.-Carlos Baraza-Calvo y Pedro-J. Gil-Vicente ha sido publicado en la revista Electronics.

Abstract

The Bose-Chaudhuri-Hocquenghem (BCH) codes are a well-known class of powerful error correction cyclic codes. BCH codes can correct multiple errors with minimal redundancy. Primitive BCH codes only exist for some word lengths, which do not frequently match those employed in digital systems. This paper focuses on double error correction (DEC) codes for word lengths that are in powers of two (8, 16, 32, and 64), which are commonly used in memories. We also focus on hardware implementations of the encoder and decoder circuits for very fast operations. This work proposes new low redundancy and reduced overhead (LRRO) DEC codes, with the same redundancy as the equivalent BCH DEC codes, but whose encoder, and decoder circuits present a lower overhead (in terms of propagation delay, silicon area usage and power consumption). We used a methodology to search parity check matrices, based on error patterns, in order to design the new codes. We implemented and synthesized them, and compared their results with those obtained for the BCH codes. Our implementation of the decoder circuits achieved reductions between 2.8% and 8.7% in the propagation delay, between 1.3% and 3.0% in the silicon area, and between 15.7% and 26.9% in the power consumption. Therefore, we propose LRRO codes as an alternative for protecting information against multiple errors.

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TFG: Desarrollo e implementación de un sistema empotrado con propiedades de tolerancia a fallos para sistemas de confort de vehículos autónomos

The student Carmelo Martínez Ruiz has succesfully defended its TFG named «Desarrollo e implementación de un sistema empotrado con propiedades de tolerancia a fallos para sistemas de confort de vehículos autónomos», co-directed by Joaquín Gracia Morán and Luis J. Saiz Adalid.

Congratulations!!!

Abstract:

In this work a study is carried out on embedded systems with fault tolerance properties by protecting the system by Error Correction Codes (ECC). The objective is to be able to implement it in autonomous vehicle comfort systems. Thus, it shows how to implement a high-efficiency ECC in an embedded system to avoid falsified measurements. Errors will be injected into the system to test the efficiency of the ECC. To show the operation of a protected system, the study of the STM32F429i-disc1 board and the DHT11 sensor will be studied in depth. Obtaining and processing the data provided by the sensor will be key, and a comprehensive explanation of how to do it will be provided. Finally, a comparison will be made between the protected system and the unprotected system, in which the reliability and precision guaranteed by the ECC in the protected system leaves no doubt that it is necessary to implement it if an acceptable level of efficiency is to be achieved.

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TFG: Desarrollo e implementación de un sistema empotrado con propiedades de tolerancia a fallos para sistemas de confort de vehículos autónomos

El alumno Carmelo Martínez Ruiz ha defendido con éxito el TFG titulado «Desarrollo e implementación de un sistema empotrado con propiedades de tolerancia a fallos para sistemas de confort de vehículos autónomos», y que ha sido co-dirigido por Joaquín Gracia Morán y Luis J. Saiz Adalid.

Enhorabuena!!!

Resumen:

En este trabajo se realiza un estudio sobre los sistemas empotrados con propiedades de tolerancia a fallos mediante la protección del sistema por Códigos de Corrección de Errores (ECC). El objetivo es el de poder implementarlo en sistemas de confort de vehículos autónomos. Así pues, se muestra cómo implementar un ECC de alta eficiencia en un sistema empotrado para evitar que salgan medidas falseadas. Se inyectarán errores en el sistema para probar la eficiencia del ECC. Para mostrar el funcionamiento de un sistema protegido, se profundizará en el estudio de la placa
STM32F429i-disc1 y del sensor DHT11. La obtención y el tratamiento de los datos proporcionados por el sensor serán claves, y se proporcionará una explicación exhaustiva de cómo hacerlo. Finalmente, se hará una comparación entre el sistema protegido y el sistema sin proteger, en el que la fiabilidad y precisión que garantiza el ECC en el sistema protegido no deja lugar a dudas de que es necesario implementarlo si se busca tener un nivel de eficiencia aceptable.

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Contribuciones para el DSN 2020

La conferencia DSN 2020, organizada por el Grupo de Sistemas Tolerantes a Fallos de la  University Politècnica de València, es un multi-conferencia que está buscando contribuciones en diferentes áreas. Más información en el siguiente enlace.

Esperamos verte en Valencia!!

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DSN 2020 Conference Tracks

DSN 2020, organized by the Fault Tolerant Systems Group of the University Politècnica de València, is a multi-track conference seeking for contributions in different tracks. More info in this link.

We hope to see you here!!

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Artículo disponible en IEEE Access

El trabajo titulado “Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection”, escrito por Luis-J. Saiz-Adalid, Joaquín Gracia-Morán, Daniel Gil-Tomás, J.-Carlos Baraza-Calvo and Pedro-J. Gil-Vicente ya está disponible en la web de IEEE Access.

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Paper available at IEEE Access

The paper entitled “Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection”, authored by Luis-J. Saiz-Adalid, Joaquín Gracia-Morán, Daniel Gil-Tomás, J.-Carlos Baraza-Calvo and Pedro-J. Gil-Vicente is available at IEEE Access.

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Artículo aceptado en IEEE Access

El trabajo titulado «Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection», escrito por Luis-J. Saiz-Adalid, Joaquín Gracia-Morán, Daniel Gil-Tomás, J.-Carlos Baraza-Calvo y Pedro-J. Gil-Vicente ha sido aceptado en la revista IEEE Access.

Resumen

Reliable computer systems employ error control codes (ECCs) to protect information from errors. For example, memories are frequently protected using single error correction-double error detection (SEC-DED) codes. ECCs are traditionally designed to minimize the number of redundant bits, as they are added to each word in the whole memory. Nevertheless, using an ECC introduces encoding and decoding latencies, silicon area usage and power consumption. In other computer units, these parameters should be optimized, and redundancy would be less important. For example, protecting registers against errors remains a major concern for deep sub-micron systems due to technology scaling. In this case, an important requirement for register protection is to keep encoding and decoding latencies as short as possible. Ultrafast error control codes achieve very low delays, independently of the word length, increasing the redundancy. This paper summarizes previous works on Ultrafast codes (SEC and SEC-DED), and proposes new codes combining double error detection and adjacent error correction. We have implemented, synthesized and compared different Ultrafast codes with other state-of-the-art fast codes. The results show the validity of the approach, achieving low latencies and a good balance with silicon area and power consumption.

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Paper accepted at IEEE Access

The paper entitled «Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection», authored by Luis-J. Saiz-Adalid, Joaquín Gracia-Morán, Daniel Gil-Tomás, J.-Carlos Baraza-Calvo and Pedro-J. Gil-Vicente has been accepted at IEEE Access.

Abstract

Reliable computer systems employ error control codes (ECCs) to protect information from errors. For example, memories are frequently protected using single error correction-double error detection (SEC-DED) codes. ECCs are traditionally designed to minimize the number of redundant bits, as they are added to each word in the whole memory. Nevertheless, using an ECC introduces encoding and decoding latencies, silicon area usage and power consumption. In other computer units, these parameters should be optimized, and redundancy would be less important. For example, protecting registers against errors remains a major concern for deep sub-micron systems due to technology scaling. In this case, an important requirement for register protection is to keep encoding and decoding latencies as short as possible. Ultrafast error control codes achieve very low delays, independently of the word length, increasing the redundancy. This paper summarizes previous works on Ultrafast codes (SEC and SEC-DED), and proposes new codes combining double error detection and adjacent error correction. We have implemented, synthesized and compared different Ultrafast codes with other state-of-the-art fast codes. The results show the validity of the approach, achieving low latencies and a good balance with silicon area and power consumption.

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